The background of the invention will be described in terms of the number of pins available on an integrated circuit. The number of transistors of a given size which can be packed onto a die of given size is directly proportional to the area of the die. In other words, a bigger silicon die gives proportionally more components. However, the number of pins which can be brought out of the package is limited by the number of bondwires which can be fastened to the die. Since the bondpads of an integrated circuit are typically arrayed around the periphery of the die, the number of bondpads grows in direct proportion to the perimeter of the die, or approximately as the square root of the area of the die. Thus, as the die grows larger, the number of package pins grows much more slowly than does the number of components.
As manufacturing technology improves, the component size of digital logic has steadily decreased. The number of components possible in a technology increases roughly as the inverse square of the lineal dimension of the components. Thus, reductions in component size allow vast increases in component count. Unfortunately, packaging technology is limited by the wire diameter which can be handled by the automated bonding machines. Wire diameter has not changed greatly over time, and so the number of wires which can be bonded to a die of given size has not increased greatly.
These facts lead to an unsettling conclusion. Despite the growth of logic component counts from approximately 100 components/die for SSI to over one million components per die for modern ASIC parts, the number of pins has increased only from 16 to perhaps 200 or so. As a result, the number of components per pin has risen from approximately 5 to about 5000. This fact places a premium on package pins. Since it seems unlikely that any revolutionary breakthrough in packaging will be made in the near future, pin count will continue to be a serious concern.
The usual solution in the prior art to integrated circuit pin limitations is to multiplex the functionality of the pins. Each pin performs multiple functions. In the case of data and address lines, multiplexing comes as a natural outgrowth of synchronous data transfer. However, many parts also require some pins to perform programming or initialization functions. For these pins, multiplexing is a much more questionable technique. The external circuitry connected to these pins should be as simple as possible; ideally simple jumpers to power supply or ground would be required. In many systems a microprocessor or microcontroller can be used to program the peripheral parts, but this requires that the peripherals be placed near the controlling chip, and this also limits the applicability of the peripheral to products not containing microprocessors or similar complex chips.
These considerations lead to the conclusion that some initialization pins cannot be multiplexed, and must instead be hard-wired to supplies, or connected to simple circuitry such as a resistor, a switch, or something of this order. For complex parts, a substantial number of initialization pins may be needed in order to convey enough information to start the system which the component controls. Since there is likely to be a premium on pins, trinary logic can be used to advantage in this situation. Trinary logic makes it possible for a single pin to receive three different input states, and therefore can extend the number of functions the pins of a device may support. For example, two trinary logic programming pins can support nine different input states, while two binary programming pins can only support four input states.
One problem that occurs in designing a trinary logic gate is that of noise margins. Noise margin problems may be best understood by first considering the common binary logic gate as an example. In a binary logic gate, one of two input voltages is recognized at a voltage input and a corresponding output is produced. The input voltage is said to be at a logic high or a logic low. Physically this means that the voltage exceeds a threshold set for a logic high, or is below a threshold set for a logic low voltage. The binary logic gate will recognize an input signal and will produce a definite response so long as the input signal satisfies the inequalities: EQU (Vi&gt;Vi.sub.H)or(Vi&lt;Vi.sub.L) [1]
Furthermore, each output generated in response to a set of inputs meeting the requirements of [1] will obey the inequalities: EQU (Vo&gt;Vo.sub.H)or(Vo&lt;Vo.sub.L) [2]
The input high voltage Vi.sub.H, input low voltage, Vi.sub.L, output high voltage Vo.sub.H and output low voltage Vo.sub.L satisfy the following inequalities: EQU Vo.sub.H &gt;Vi.sub.H &gt;VI.sub.L &gt;Vo.sub.L [ 3]
A pair of noise margins NM.sub.H and NM.sub.L are defined in terms of the above quantities: EQU NM.sub.H =Vo.sub.H -Vi.sub.h EQU NM.sub.L =Vi.sub.L -Vo.sub.L [ 4]
The noise margins can be seen as a measure of the noise immunity of the binary gate. So long as the level of noise on a high-level signal never exceeds NM.sub.H, and the level of noise on a low-level signal never exceeds NM.sub.L, the gates of the system will operate reliably. It follows that the separation of Vo.sub.H and Vo.sub.L should be as large as possible, while the separation of Vi.sub.H and Vi.sub.L (the transition region of the gate) should be as small as possible. The relationships described above are graphically illustrated in FIG. 1.
Binary logic defines only two states, a high state (Vi&gt;Vi.sub.H, Vo&gt;Vo.sub.H) and a low state (Vi&lt;Vi.sub.L, Vo&lt;Vo.sub.L). It is possible to define logic families with more than two states, such as the one referred to herein as trinary logic, which incorporates three states. Trinary logic gates will recognize a signal and will produce a definite response as long as: EQU (Vi&gt;Vi.sub.H) or (Vi&lt;Vi.sub.M2 and Vi&gt;Vi.sub.M1) or (Vi&lt;Vi.sub.L)[5]
Furthermore, outputs generated in response to a set of inputs obeying the above inequality will satisfy the inequalities: EQU (Vo&gt;Vo.sub.H) or (Vo&lt;Vo.sub.M2 and Vo&gt;Vo.sub.M1) or (Vo&lt;Vo.sub.L)[6]
The output and input voltages must satisfy the following inequality: EQU Vo.sub.H &gt;Vi.sub.H &gt;Vi.sub.M2 &gt;Vo.sub.M2 &gt;Vo.sub.M1 &gt;Vi.sub.M1 &gt;Vi.sub.L &gt;Vo.sub.L [ 7]
Four noise margins can be defined for trinary logic, in a manner analogous to binary logic. These are as follows: EQU NM.sub.H =Vo.sub.H -Vi.sub.H EQU NM.sub.M2 =Vi.sub.M2 -Vo.sub.M2 EQU NM.sub.M1 =Vo.sub.M1 -Vi.sub.M1 EQU NM.sub.L =Vi.sub.L -Vo.sub.L [ 8]
FIG. 2 depicts these relationships in a graphical form. The inequality of equation [8] indicates that there is a middle range of inputs that has to be recognized by a trinary input gate, in addition to the high and low voltages. The existence of four noise margins in trinary logic implies that the noise immunity of this logic for a given voltage range may be less than that of binary logic. This is not necessarily true, as a more complete analysis of noise presented in a later section will show. However, the additional complexity of trinary logic does place it at a significant disadvantage when compared to binary logic. For this reason, little trinary logic (or any higher-order logic) has been used.
There are several approaches in the prior art to providing a trinary logic input capability. A simple prior art trinary input logic gate which meets many of the above requirements is shown in FIG. 3. The circuit 1 consists of a PMOS-logic inverter comprised of transistor 3 and current source 5 and an NMOS-logic inverter comprised of transistor 7 and current source 9 which are both connected to the input, Vin, and which generate separate binary outputs Vo1 and Vo2. The current sources are fabricated by any means available in the process, for example current mirrors driven by a bias circuit, or depletion-mode loads, or even simple resistive loads could be used.
The truth table also shown in FIG. 3 depicts the logical operation of the logic gate 1 for three input voltages. If the input at the Vin terminal is a low voltage, the outputs are both high. If the input at the Vin terminal is a high voltage, the outputs are both low. If the input is driven to a midrange voltage, the output is high for the PMOS gate and low for the NMOS gate, that is both output transistors are on.
The input voltage thresholds of the circuit 1 depicted in FIG. 3 are relatively easy to calculate. Suppose, for the purposes of analysis, that current sources 5 and 9 are perfect current sources. Transistors 3 and 7 are MOSFETs described by the Shichman-Hodges equation: ##EQU1## where k is the transconductance of the MOS transistor (k'.multidot.W/L), and Vt is the threshold voltage of the transistor.
Suppose that the output Vo1 of the PMOS gate has a transition point at 1/2 of the supply voltage V.sub.dd ; that is to say that Vi.sub.H and Vi.sub.L of the following binary gate will (neglecting process shifts) both be set at 1/2 the supply. This is a transition voltage compatible with common CMOS logic. Then, at the point where the PMOS inverter switches the following binary gate, transistor 3 can be assumed to be operating in saturation. The input voltage necessary to reach this transition point is then: ##EQU2##
This equation can be interpreted as a best-case value for Vi.sub.H and Vi.sub.M2 for the trinary input (process variations will, of course, cause shifts which will force Vi.sub.M2 to be lower, and Vi.sub.H to be higher, than Vin(H)). A similar analysis can be performed for the NMOS inverter: ##EQU3##
This equation can be interpreted as a best-case value for Vi.sub.L and Vi.sub.M1 for the trinary input.
The noise margins for the above gate are dependent upon supply voltage. The voltages Vin(L) and Vin(H) are both on the order of 1-2V for typical digital MOS transistors, so a supply voltage of 5V will give roughly equal values for all noise margins of the trinary gate. A 3V power supply will not operate the trinary gate with satisfactory noise margins, which severely limits its applicability to modern digital systems. This is unsurprising, as trinary logic inherently has noise margin limitations which are more severe than those imposed upon binary logic. Another limitation of the prior art gate 1 of FIG. 3 is that it requires a mid-range supply to generate the mid-state (M in the logic table of FIG. 3). A mid-range supply is not necessarily available, especially in an all-digital system. This gate offers simplicity and small size, as it can be implemented in four transistors if depletion loads are available, and it is compatible with many processes including pure digital CMOS processes. It also offers relatively low supply currents, depending upon the values chosen for I.sub.1 and I.sub.2. However, due to limited noise margins, inability to operate from 3V logic, and the need for a mid-range supply, it is clearly unsuitable for use with all digital CMOS applications, especially where a low supply voltage is to be used.
A second prior art design approach to a trinary logic input gate is depicted in FIG. 4. In FIG. 4, gate 11 comprises a resistive voltage divider of resistors 13 and 15 coupled to the input terminal Vin, a PMOS inverter circuit made up of PMOS transistor 19 and current source 17, and an NMOS inverter circuit made up of NMOS transistor 23 and current source 21. Again, the circuit outputs a PMOS output voltage Vo1, and an NMOS output voltage Vo2. Although the truth table is not repeated, this circuit operates logically in exactly the same manner as the circuit of FIG. 3.
In operation, the resistors of FIG. 4 provide the mid-range voltage Vm to the input terminal when the input is not craven. Otherwise, the operation of the circuit of FIG. 4 is exactly the same as that in FIG. 3. It could be argued that this circuit implementation solves the problems associated with the circuit of FIG. 3. While this is true in some respects, resistors have a number of severe disadvantages, especially in terms of integrated circuit implementations. In order to limit the current consumption of the gate 11 to a reasonable value, the resistors 13 and 15 must have very large values. For example, to limit the current flow to 5 .mu.A with a supply of 5V, a total of one megohm of resistance is required. In a typical CMOS process, where resistors are fabricated from gate polysilicon with a sheet resistance of about 10 Ohms/square, this means that some 100,000 squares of resistance material would be required, which would require vast amounts of silicon area. Also, resistors are not compatible with all semiconductor processes. For example, a dad-gate CMOS process may have no suitable polysilicon resistors, forcing so-called well resistors to be used; these may be extremely large and therefore impracticable. Also, use of a resistor bias network ensures that Idd will vary with Vdd, which is undesirable for input gates which may operate over a wide range of voltages. For instance, a gate which is designed to operate over the voltage range 3&lt;V.sub.dd &lt;15V will exhibit a 5:1 variation of supply current over the voltage range. This variation with power supply results in excessive and undesirable power consumption at the high end of the supply voltage range.
The prior art circuits of FIGS. 3 and 4 are typical of existing implementations of trinary input gates, and illustrate the severe shortcomings of the existing implementations. Other more complicated solutions have also been attempted. For example, U.S. Pat. No. 5,198,202, issued Mar. 30, 1993. and entitled "Integrated Circuit with Mode Detection Pin for Tristate Level Detection", and herein incorporated by reference, discloses a circuit for detecting a high impedance or undriven condition at an input pin. This circuit requires not only an internal resistor, but also four switches, sequencing circuitry for controlling the switches, a memory with at least two locations, and a two bit to three bit decoder for outputting the result. Additionally, the input signal is required to remain in a given state for a relatively long period, as the sequencer must operate the switches into two different positions and sample the input into the two memory locations before a determination of the voltage at the input can be made. An alternative prior art approach, but no less complex, is described in U.S. Pat. No. 5,212,800, issued May 18, 1993, and entitled "Method and Apparatus for Sensing Trinary Logic States in a Microcomputer using Bus Holding Circuits". In this approach, a pair of tristate buffers is required and are coupled to the input and the output, respectively, of a binary latch memory. The condition of the input is used to determine whether the output should be driven to a high or a low logic voltage, or tristated itself. Again, this approach requires a substantially long time to make a determination as to the voltage at the input, and many components, which require area on the silicon substrate and power to operate. None of the prior art solutions described above provides a practical trinary input gate.
A need for a simple trinary input gate which can be used to decode trinary-logic input pins for integrated circuits and which is compatible with CMOS semiconductor process steps without the need for additional masks or processing steps thus exists.